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w9412fada 128mb (16m 64) ddr sdram dimm publication release date: march 1 4 , 2002 - 1 - revision a1 1. general descripti on the winbond w9412fada series are 16m x 64 double data rate synchronous dynamic ram (ddr sdram) memory modules. these modules consists of four pieces of w942516ah (64m x 16 bits) ddr sdrams and assembled on a jedec standard 184 - pin di mm pcb. to provide high data bandwidth, w9412fada uses a double data rate architecture to transfer two data words per clock cycle and delivers a data bandwidth of up to 2.1g (ddr266) bytes per second. it is ideal for high performance systems that require f ast data transfer memory modules. by reading the serial presence - detect (spd), the system can identify the module type, ddr sdram timing parameters and other necessary information to optimize system setting and maximize its performance. 2. features jedec standard 184 - pin dual in - line memory module (dimm) comply to ddr266 and ddr200 specification differential clock inputs (clk and clk ) double data rate architecture, two data transfers per clock cycle cas latency: 2 and 2.5 bur st lengths: 2, 4, 8 auto refresh and self refresh 8k refresh cycles / 64 ms serial presence detect with eeprom interface: sstl - 2 power supply: 2.5v 0.2v pcb height: 1.25 inches 3. available part nu mbers module part number speed w9412fada - 7 d dr266/cl2 w9412fada - 75 ddr266/cl2.5
w9412fada - 2 - 4. pin assignment pin font pin font pin font pin back pin back pin back 1 vref 32 a5 62 v dd q 93 v ss 124 v ss 154 ras 2 dq0 33 dq24 63 we 94 dq4 125 a6 155 dq45 3 v ss 34 v ss 6 4 dq41 95 dq5 126 dq28 156 v dd q 4 dq1 35 dq25 65 cas 96 v dd q 127 dq29 157 cs0 5 dqs0 36 dqs3 66 v ss 97 dqs9 128 v dd q 158 cs1 6 dq2 37 a4 67 dqs5 98 dq6 129 dqs12 159 dqs14 7 v dd 38 v dd 68 dq42 99 dq7 130 a3 160 v ss 8 dq3 39 dq26 69 dq43 100 v ss 131 dq30 161 dq46 9 nc 40 dq27 70 v dd 101 nc 132 v ss 162 dq47 10 nc 41 a2 71 *s2 102 nc 133 dq31 163 *s3 11 v ss 42 v ss 72 dq48 103 *a13 134 *cb4 164 v dd q 12 dq8 43 a1 73 dq49 104 v dd q 135 *cb5 165 d q52 13 dq9 44 *cb0 74 v ss 105 dq12 136 v dd q 166 dq53 14 dqs1 45 *cb1 75 clk2 106 dq13 137 clk0 167 nc 15 v dd q 46 v dd 76 clk2 107 dqs10 138 clk0 168 v dd 16 ckl1 47 *dqs8 77 v dd q 108 v dd 139 v ss 169 dqs15 17 clk1 48 a0 78 dqs6 109 dq14 140 *dqs17 170 dq54 18 v ss 49 *cb2 79 dq50 110 dq15 141 a10 171 dq55 19 dq10 50 v ss 80 dq51 111 cke1 142 *cb6 172 v dd q 20 dq11 51 *cb3 81 v ss 112 v dd q 143 v dd q 173 nc 21 cke0 52 ba1 82 v dd id 113 *ba2 144 *cb7 174 dq60 22 v dd q key 83 dq56 114 dq20 key 175 dq61 23 dq16 53 dq32 84 dq57 115 a12 145 v ss 176 vss 24 dq17 54 v dd q 85 v dd 116 v ss 146 dq36 177 dqs16 25 dqs 55 dq33 86 dqs7 117 dq21 147 dq37 178 dq62 26 v ss 56 dqs4 87 dq58 118 a11 148 v dd 179 dq63 27 a9 57 dq34 88 dq59 119 dqs11 149 dqs13 180 v dd q 28 dq18 58 v ss 89 v ss 120 v dd 150 dq38 181 sa0 29 a7 59 ba0 90 wp 121 dq22 151 dq39 182 sa1 30 v dd 60 dq35 91 sda 122 a8 152 v ss 183 sa2 31 dq19 61 dq40 92 scl 123 dq23 153 dq44 184 v dd spd *these pins are n ot used in this module.
w9412fada publication release date: march 1 4 , 2002 - 3 - revision a1 5. pin descriptions pin name function description clkn, clkn clock input clkn and clkn are differential clock inputs. all input command signals are sampled at the positive edge of clk (except for dq, dm and cke). csn chip select disable or enable the command decoder. when command decoder is disabled, new command is ignored and previous operation continues. cken clock enable cke controls the clock activation and deactivatio n. when cke is low, power down mode, suspend mode, or self - refresh mode is entered. a0 - a12 address multiplexed pins for row and column address. row address: a0 - a12. column address: a0 - a8. ba0 - ba1 bank select address selects bank to be activated d uring row address latch time. selects bank for read/write during column address latch time. ras row address strobe command input. when sampled at the rising edge of the clock, ras , cas and we define the operation to be executed. cas column address strobe referred to ras we write enable referred to ras dm0 - dm7 input/output mask the output buff er is placed at hi - z when dm is sampled high in read cycle. in write cycle, sampling dm high will block the write data. dq0 - dq63 data input/output multiplexed pins for data output and input dqs0 - dqs7 data strobe input/output output with read data, in put with write data. dqs is edge - aligned with read data, centered in write data. v dd power (+2.5v) power supply (2.5v). v ss ground ground v ref reference voltage sstl - 2 reference voltage v dd spd spd power separated power supply for spd eeprom (2.3v - 3. 6v) scl serial clock clock for serial presence detection sda serial data i/o data line for serial presence detection san spd address line system assigned address (sa0 - sa2) to identify different memory module in a system board. nc no connection no con nection
w9412fada - 4 - 6. block diagram u1 ldm udm ldqs udqs u2 ldm udm ldqs udqs u3 ldm udm ldqs udqs u4 ldm udm ldqs udqs dq (16:23) 22 dq (24:31) 22 dqs3 22 dm3 22 dm2 22 dqs2 22 dq (0:7) 22 dq (8:15) 22 dqs1 22 dm1 22 dm0 22 dqs0 22 dq (32:39) 22 dq (40:47) 22 dqs5 22 dm5 22 dm4 22 dqs4 22 dq (48:52) 22 dq (56:63) 22 dqs7 22 dm7 22 dm6 22 dqs6 22 cs0 dq (8:15) dq (0:7) cs cs dq (0:7) dq (8:15) dq (8:15) dq (0:7) cs cs dq (0:7) dq (8:15) a0 ~ a13, ba0 & 1 sdrams u1 ~ u4 ras cas we sdrams u1 ~ u4 sdrams u1 ~ u4 sdrams u1 ~ u4 sda scl u7 a0 a1 a2 serial pd sa0 sa1 sa2 wp sda v ddid v dd spd v dd /v ddq v ref v ss spd d0~d7 d0~d7 d0~d7
w9412fada publication release date: march 1 4 , 2002 - 5 - revision a1 7. absolute maximum ratings symbol parameter rating unit v in input voltage - 0.3 to v dd +0.3 v v out output voltage - 0.3 to v dd +0.3 v v dd power supply voltage - 0.3 - 4.6 v t opr operating tempe rature 0 to 70 c t stg storage temperature - 55 to 125 c pd power dissipation 4 w i out short circuit output current 50 ma note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. 8. recommended dc op erating conditions c) parameter symbol min. typ. max. unit notes power supply voltage v dd 2.3 2.5 2.7 v 2 power supply voltage (for i/o buffer) v dd q 2.3 2.5 v dd v 2 input reference voltage v ref 0.49 x v dd q 0 .50 x v dd q 0.51 x v dd q v 2,3 termination voltage (system) v tt v ref - 0.04 v ref v ref +0.04 v 2,8 input high voltage (dc) v ih (dc) v ref +0.15 - v dd q +0.3 v 2 input low voltage (dc) v il (dc) - 0.3 - v ref - 0.15 v 2 differential clock dc input voltage v ick (d c ) - 0.3 - v dd q +0.3 v 15 input differential voltage. clk and clk inputs (dc) v id (dc) 0.36 - v dd q +0.6 v 13,15 input high voltage (ac) v ih (ac) v ref +0.31 - - v 2 input low voltage (ac) v il (ac) - - v ref - 0.31 v 2 input differential voltage. clk and clk inputs (ac) v id (ac) 0.7 - v dd q +0.6 v 13,15 differential ac input cross point voltage vx (ac) v dd q/2 - 0.2 - v dd q/2 +0.2 v 12, 15 differential clock ac middle point v iso (ac) v dd q/2 - 0.2 - v dd q/2 +0.2 v 14, 15 not e: undershoot limit: v il (min) = - 0.9v with a pulse width < 5 ns overshoot limit: v ih (max) = v dd q +0.9v with a pulse width < 5 ns v ih (dc) and v il (dc) are levels to maintain the current logic state, v ih (ac) and v il (ac) are levels to change to the new l ogic state.
w9412fada - 6 - 9. capacitance (v dd = v dd q = 2.5v 0.2v, f = 1 mhz, t a = 25 c, v out (dc) = v dd q/2, v out (peak to peak) = 0.2v) parameter symbol min. max. unit address input capacitance (a0 - a12, ba0, ba1) c add - in 12 pf command input capacitance ( ras , cas , we ) c cmd - in 12 pf cs signals input capacitance ( cs0 ) c cs - in 12 pf cke signal input capacitance (cke0) c cke - in 12 pf clk signals input capacitance ( cl kn, clkn ) c clk - in 6 pf dm/dqs/dq input capacitance (dm0 - dm7, dqs0 - 7, dq0 - 63) c i/o 5 pf 10. dc characteristi cs max. unit notes parameter sym. - 7 - 75 operating current: one bank active - precharge; t rc = t rc min; t ck = t ck mi n; dq, dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle i dd0 440 440 7 operating current: one bank active - read - precharge; burst = 2; t rc = t rc min; cl=2.5; t ck = t ck min; i out = 0ma; address and c ontrol inputs changing once per clock cycle. i dd1 440 440 7, 9 precharge - power - down standby current: all banks idle; power down mode; cke < v il max; t ck = t ck min; vin = v ref for dq, dqs and dm i dd2p 8 8 idle floating standby current: cs > v ih min; all banks idle; cke > v ih min; address and other control inputs changing once per clock cycle; vin = vref for dq, dqs and dm i dd2f 180 160 7 idle standby current: cs > v ih min; all banks idle; cke > v ih min; t ck = t ck min; ad dress and other control inputs changing once per clock cycle; vin > v ih min or vin < v il max for dq, dqs and dm i dd2n 180 160 7 idle quiet standby current: cs > v ih min; all banks idle; cke > v ih min; t ck = t ck min; address and other contr ol inputs stable; vin > v ref for dq, dqs and dm i dd2q 160 140 ma 7 active power - down standby current: one bank active; power down mode; cke < v il max; t ck = t ck min i dd3p 80 80 active standby current: cs > v ih min; cke > v ih min; one ban k active - precharge; t rc = t ras max; t ck = t ck min; dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd3n 280 260 7 operating current: burst = 2; reads; continuous burst; one bank active ; address and control inputs changing once per clock cycle; cl=2.5; t ck = t ck min; i out = 0ma i dd4r 660 620 7, 9 operating current: burst = 2; write; continuous burst; one bank active; address and control inputs changing once per clock cycle; cl = 2.5; t ck = t ck min; dq, dm and dqs inputs changing twice per clock cycle i dd4w 660 620 7 auto refresh current: t rc = t rfc min i dd5 760 760 7 self refresh current: cke < 0.2v i dd6 12 12 random read current: 4 banks active read with activate every 20ns, aut o - precharge read every 20ns; burst = 4; t rcd = 3; i out = 0ma; dq, dm and dqs inputs changing twice per clock cycle; address changing once per clock cycle i dd7 108 0 108 0
w9412fada publication release date: march 1 4 , 2002 - 7 - revision a1 11. ac characteristi cs of sdram componen ts (notes: 10, 12) symbol parameter - 7 - 75 u nits notes min. max. min. max. t rc active to ref/active command period 65 65 t rfc ref to ref/active command period 75 75 t ras active to precharge command period 45 100000 45 100000 t rcd active to read/write command delay time 15 15 t rap active to read with auto precharge enable 15 15 ns t ccd read/write(a) to read/write(b) command period 1 1 t ck t rp precharge to active command period 20 20 t rrd active(a) to active(b) command period 15 15 t wr write recovery time 15 15 t dal auto precharge write recovery + precharge time 30 30 t ck cl=2 7.5 15 8 15 clk cycle time cl=2.5 7 15 7.5 15 t ac data access time from clk, clk - 0.75 0.75 - 0.75 0.75 t dqsck dqs output access time from cl k, clk - 0.75 0.75 - 0.75 0.75 16 t dqsq data strobe edge to output data edge skew 0.5 0.5 ns t ch clk high level width 0.45 0.55 0.45 0.55 11 t cl clk low level width 0.45 0.55 0.45 0.55 t ck t hp clk half period (minimum of actual t ch, t cl ) min. (t cl ,t ch ) min. (t cl ,t ch ) t qh dq output data hold time from dqs t hp - 0.75 t hp - 0.75 ns t rpre dqs read preamble time 0.9 1.1 0.9 1.1 11 t rpst dqs read postamble time 0.4 0.6 0.4 0.6 t ck t ds dq and dm setup time 0.5 0.5 t d h dq and dm hold time 0.5 0.5 t dipw dq and dm input pulse width (for each input) 1.75 1.75 ns t dqsh dqs input high pulse width 0.35 0.35 11 t dqsl dqs input low pulse width 0.35 0.35 t dss dqs falling edge to clk setup time 0.2 0.2 t dsh dqs falling edge hold time from clk 0.2 0.2 t ck t wpres clock to dqs write preamble set - up time 0 0 ns t wpre dqs write preamble time 0.25 0.25 11 t wpst dqs write postamble time 0.4 0.4 t dqss write command to first dqs latching tra nsition 0.75 1.25 0.75 1.25 t dssk udqs ? ldqs skew (x 16) - 0.25 0.25 - 0.25 0.25 t ck t is input setup time 0.9 0.9 t ih input hold time 0.9 0.9 t ipw control & address input pulse width (for each input) 2.2 2.2 t hz data - out high - impedance time from clk, clk - 0.75 0.75 - 0.75 0.75 t lz data - out low - impedance time from clk, clk - 0.75 0.75 - 0.75 0.75 t t(ss) sstl input transition 0.5 1.5 0.5 1.5 ns t wtr internal write to read command delay 1 1 t ck t xsnr exit self refresh to non - read command 75 75 ns t xsrd exit self refresh to read command 10 10 t ck t ref refresh time (8k) 64 64 ms t mrd mode register set cycle time 15 15 ns
w9412fada - 8 - 12. ac test conditio n of sdram component s symbol parameter value unit note v ih input high voltage (ac) v ref +0.31 v v il input low voltage (ac) v ref - 0.31 v v ref input reference voltage 0.5 x v ddq v v tt termination voltage 0.5 x v ddq v v swing input signal peak to peak swing 1.0 v v r differential cloc k input reference voltage v x (ac) v v id (ac) input difference voltage. clk and clk inputs (ac) 1.5 v slew input signal minimum slew rate 1.0 v/ns v otr output timing measurement reference voltage 0.5 x v ddq v v swing (max) v dd q v ss t t v ih min (ac) v ref v il max (ac) slew = (v ih min (ac) - v il max (ac)) / t r t = 50 ohms vtt a.c. test load (a) z = 50 ohms output 30pf notes: (1) conditions outside the limits listed under ?absolute maximum ratings? may cause permanent damage to the device . (2) all voltages are referenced to v ss , v ss q . (3) peak to peak ac noise on v ref may not exceed 2%of v ref(dc). (4) v oh = 1.95v,v ol = 0.35v (5) v oh = 1.9v,v ol = 0.4v (6) the values of i oh(dc) is based on v dd q = 2.3v and v tt = 1.19v. the values of i ol(dc) is based on v dd q = 2.3v and v tt = 1.11v. (7) these parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of t ck and t rc . (8) v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref and must track variations in the dc level of v ref .
w9412fada publication release date: march 1 4 , 2002 - 9 - revision a1 (9) these parameters depend on the output loading. specified values are obtained with the output open. (10) transition times are measured between v ih min(ac) and v il max(ac) .transition (rise and fall) of input signals have a fixed slope. (11) if the result of nominal calculation with r egard to t ck contains more than one decimal place, the result is rounded up to the nearest decimal place. i.e., t dqss =0.75 t ck , t ck =7.5ns, 0.75 7.5ns = 5.625ns is rounded up to 5.6ns. (12) v x is the differential clock cross point voltage where input timing me asurement is referenced. (13) v id is magnitude of the difference between clk input level and clk input level. (14) v iso means {v ick (clk) + v ick ( clk )}/2. (15) refer to the figure below. clk clk v ss v ick v x v x v x v x v x v ick v ick v ick v id(ac) v i d(ac) 0 v differential v iso v iso(min) v iso(max) v ss (16) t ac and t dqsck de pend on the clock jitter. these timing are measured at stable clock.
w9412fada - 10 - 13. operation modes the following simplified truth table illustrates the operation modes of ddr sdram. for more detailed information please refer to the ddr sdram datasheet. table 1: sim plified truth table command device state cke n - 1 cke n dm n bs0, bs1 a10 a12, a11, a9 - a0 cs ras cas we bank active idle h x x v v v l l h h bank precharge any h x x v l x l l h l precharge all any h x x x h x l l h l write active (3) h x x v l v l h l l write with autoprecharge active (3) h x x v h v l h l l read active (3) h x x v l v l h l h read with autoprecharge active (3) h x x v h v l h l h mode register set idle h x x l, l c c l l l l extended mode register set idle h x x h, l v v l l l l no operation any h x x x x x l h h h burst read stop active h x x x x x l h h l device deselect any h x x x x x h x x x auto refresh idle h h x x x x l l l h self refresh entry idle h l x x x x l l l h h x x x self refresh exit idle (self refresh) l h x x x x l h h x h x x x power down mode entry idle/ active (5) h l x x x x l h h x h x x x power down mode exit any (power down) l h x x x x l h h x da ta write enable active h x l x x x x x x x data write disable active h x h x x x x x x x notes: 1. v = valid x = don?t care l = low level h = high level 2. cke n signal is input level when commands are issued. 3. cke n - 1 signal is input level one clock cycle bef ore the commands are issued. 4. these are state designated by the bs0,bs1 signals. 5. power down mode can not entry in the burst cycle.
w9412fada publication release date: march 1 4 , 2002 - 11 - revision a1 14. serial presence detect eeprom the serial presence detect (spd) function is implemented by using a 2,408 - bit eeprom compon ent. this nonvolatile storage device contains those data for identifying the module type and various sdram organizations and timing parameters. system read operations to the eeprom device occur using the dimm scl(clock) and sda (data) signals, together wit h sa(2:0) which provide the eeprom device address. spd eeprom dc operating conditions (vcc=2.3v ~ 3.6v) parameter/condition symbol min. max. unit notes supply voltage v cc 2.3 3.6 v input high (logic 1) voltage, all inputs v ih v cc x 0.7 v cc +0.5 v inpu t low (logic 0) voltage, all inputs v il - 0.3 v cc x 0. 3 v output low voltage, lout = 3 ma v ol 0.4 v i ol = 3 ma input leakage current, v in = gnd to v cc i li 2 m a output leakage current, v out = gnd to v cc i lo 2 m a power supply current scl clock frequ ency =100 khz i cc 1 ma spd ac operating conditions (vcc = 2.3v ~ 3.6v) parameter sym. min. max. unit scl clock frequency f scl 100 khz noise suppression time constant at scl, sda inputs t i 100 ns scl low to sda data out valid t aa 0.2 3.5 m s time th e bus must be free before a new transition can start t buf 4.7 m s start condition hold time t hd:sta 4.0 m s clock low period t low 4.7 m s clock high period t high 4.0 m s start condition setup time t su:sta 4.7 m s data in hold time t hd:dat 0 m s data in setup time t su:dat 250 ns sda and scl rise time t r 1 m s sda and scl fall time t f 300 ns stop condition setup time t su:sto 4 m s data out hold time t dh 200 ns write cycle time t wr 10 ms note: the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. during the write cycle the eeprom bus interface circuits are disabled, sda is allowed to remain high the bus level pull - up resistor, and the device does not respond to its slave address.
w9412fada - 12 - 15. spd data function supported hex value byte no. function described - 7 - 75 - 7 - 75 0 defines # bytes written into serial memory at module manufacturer 128 bytes 80h 1 total # bytes of spd memory device 256 bytes (2k - bit) 08h 2 fundam ental memory type (fpm, edo, dram..) ddr sdram 07h 3 # row addresses on this assembly 13 0dh 4 # column addresses on this assembly 09 09h 5 # module rows on this assembly 1 row 01h 6 data width of this assembly. 64 bits 40h 7 data width continuation - 00h 8 voltage interface standard of this assembly sstl 2.5v 04h 9 sdram cycle time @cas latency of 2.5 7 ns 7.5 ns 70h 75h 10 sdram access time @cas latency of 2.5 +/ - 0.75 ns +/ - 0.75 ns 75h 75h 11 dimm configuration type (non - parity, parity ecc) non p arity 00h 12 refresh rate/type 7.8 us, support self refresh 82h 13 sdram width, primary dram x 16 10h 14 error checking sdram data width none 00h 15 minimum clock delay, back random column addresses tccd = 1 clk 01h 16 burst lengths supported 2, 4, 8 0eh 17 #bank on each sdram device 4 banks 04h 18 cas# latencies supported 2 & 2.5 0ch 19 cs# latency 0 clk 01h 20 write latency 1 clk 02h 21 sdram module attributes differential clock, non - buffered non ? registered & redundant addressing 20h 22 sdram d evice attributes: general 2.5v+/ - 10% voltage tolerance, burst read, write, precharge all, auto precharge 00h 23 sdram cycle time @ cas latency of 2 7.5 ns 10 ns 75h a0h 24 sdram access time @cas latency of 2 +/ - 0.75 ns +/ - 0.75 ns 75h 75h 25 sdram cycle time @ cas latency of 1.5 - - 00h 00h 26 sdram access time @cas latency of 1.5 - - 00h 00h 27 precharge to active command period (t rp ) 20 ns 20 ns 50h 50h 28 active to active command period (t rrd ) 15 ns 15 ns 3ch 3ch 29 active to read/write command del ay time (t rcd ) 20 ns 20 ns 50h 50h 30 minimum active to precharge period (t ras ) 45 ns 45 ns 2dh 2dh 31 density of each row on module each row of 128 mb 20h 32 command and address signal input setup time 0.9 ns 0.9 ns 90h 90h 33 command and address sign al input hold time 0.9 ns 0.9 ns 90h 90h 34 data signal input setup time 0.5 ns 0.5 ns 50h 50h 35 data signal input hold time 0.5 ns 0.5 ns 50h 50h 36 - 61 superset information (may be used in future) - 00h 62 spd data specification revision initial r elease revision 00h 63 checksum for bytes 0 - 62 - - 76h a6h 64 - 128 unused storage locations - 00h
w9412fada publication release date: march 1 4 , 2002 - 13 - revision a1 16. labeling informa tion there is a product description sticker stuck on each module to fully describe the information of the module. the following are examples of the product description sticker. examples: module p/n example of sticker w9412fada - 7 (ddr266/cl2 dimm) w9412fada - 7 128mb ddr266/cl2 dimm taiwan 126k264896 w9412fada - 75 (ddr266/cl2.5 dimm) w9412fada - 75 128mb ddr266/cl2.5 dimm taiwan 126k264896 the content of this product description sticker is described as below: 1. module part number w9412fada - 7/ - 75 dimm module part number informatoin w94 winbond product line w94: ddr sdram memory size 12: 128mbytes ddr sdram type f: 16m x 16 speed grade -7: ddr266 cl2 -75: ddr266 cl2.5 module version a: a version module type d: ddr dimm ddr sdram version a: a version 12 f a d a -7/-75 2. total memory size: 128mbytes 3. compliant industry spec: ddr266/cl2, ddr266/cl2.5 4. module type: dimm 5. manufacturing loca tion: taiwan 6. tracking number: 126k264896 (the number ?126k264896? is for reference only. it is changed according to assembly date, assembly site, and serial lot number.)
w9412fada - 14 - 17. package dimensio ns 0.394 1.250 0.70 0.157 0.098 5.25 units:inches tolerances: .005 unless othrerwise specified component p/n: w942516ah-7/-75 (16m x 16 ddr-sdram,tsop-66) front view rear view 0.125 max 0.050 .004 spd
w9412fada publication release date: march 1 4 , 2002 - 15 - revision a1 headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5665577 http://www.winbond.com.tw/ taipei office tel: 886-2-8177-7168 fax: 886-2-8751-3579 winbond electronics corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 winbond electronics (h.k.) ltd. no. 378 kwun tong rd., kowloon, hong kong fax: 852-27552064 unit 9-15, 22f, millennium city, tel: 852-27513100 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. winbond electronics (shanghai) ltd. 200336 china fax: 86-21-62365998 27f, 2299 yan an w. rd. shanghai, tel: 86-21-62365999 winbond electronics corporation japan shinyokohama kohoku-ku, yokohama, 222-0033 fax: 81-45-4781800 7f daini-ueno bldg, 3-7-18 tel: 81-45-4781881 9f, no.480, rueiguang rd., neihu chiu, taipei, 114, taiwan, r.o.c.

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